The present invention relates to a semiconductor device having 3-dimensional structure and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device wherein passive elements, such as, inductors, capacitors, micro-switches, and waveguides, are formed over an integrated circuit (IC) which is arranged on the substrate.
Conventional integrated circuit technology was begun from U.S. Pat. No. 3,138,743, which was issued to J. S. Kilby in 1964. The ""743 patent discloses a technique for integrating various electronic devices, including passive elements, over a planar semiconductor substrate. According to the ""743 patent, passive elements are integrated on the planar surface of a semiconductor substrate. Therefore, size of a manufactured chip was large. Moreover, the passive elements suffered from the parasitic effects from the substrate since they were in contact with the substrate. These problems become noticeable when the technique is applied to radio-frequency (RF) lCs.
Recently, many RF lCs employ off-chip passive elements which are disposed outside of the chip. The off-chip passive elements, however, increase size of an overall system. Also, cost for fabricating the overall system increases when the off-chip passive elements are employed.
Even manufactured by the conventional integrated circuit technology, resistors and capacitors may satisfy the requirements of present IC applications. However, the integration of inductors has been unsuccessful for a long time.
Conventional integrated inductors were mainly planar-type spiral inductors. The spiral inductors occupy large area on a substrate. Moreover, the area of an inductor, whose inductance value satisfies the requirement for general high-frequency devices, should be larger than any other passive elements and even larger than active devices such as a transistor. Further, the conventional spiral inductor inevitably has substrate loss, which stems from parasitic effects due to the contact with a substrate. Also, the thickness of a metal line, which can be formed by the conventional integration technique, cannot exceed 5 xcexcm. Therefore, the conventional spiral inductor has high series resistance and small capacity of current flow. Large series resistance and substrate loss decreases the quality (Q) factor, which is one of the most important characteristics for an inductor, and reduces the frequency where maximum Q factor occurs.
It is known to improve quality of a spiral inductor which is formed in an oxide layer overlying a silicon substrate, by selectively removing the silicon material underneath the inductor to reduce parasitic capacitance. This technique of removing silicon material underneath an inductor is disclosed in U.S. Pat. No. 5,539,241, issued on Jul. 23, 1996 to A. A. Abidi, et al., U.S. Pat. No. 5,773,870, issued on Jun. 30, 1998 to S. Su et al., and U.S. Pat. No. 5,844,299, issued on Dec. 1, 1998 to R. B. Merrill, et al. The three patents, however, did not allow integration of circuit underneath the inductor. Therefore, additional area for the circuit is necessary. Moreover, the process of removing the substrate underneath an inductor does not compatible with the process of integrating a circuit.
As an another technique, it is known to insert a thick layer of dielectric material, such as, polyimide, between an inductor and substrate to reduce parasitic capacitance to the substrate. This technique is employed in U.S. Pat. No. 5,478,773, issued on Dec. 26, 1995 to S. D. Chandler, et al. and U.S. Pat. No. 5,804,043, issued on Sep. 8, 1998 to l. J. Bahl.
The ""773 patent suggested that resistance of an inductor could be reduced by using copper of several xcexcm thickness as material for the inductor. The ""773 patent suggested that the polyimide may have thickness of 1 xcexcm or greater. Contrary to the ""773 patent, however, it is expected that a thickness of several tens xcexcm is required, in order to prevent the inductor from affecting the integrated circuit therebelow. Further, the ""773 patent has limitation that temperature of the process for forming the dielectric layer should not affect the integrated circuit therebelow.
As an another technique, a method of floating an inductor over a substrate was suggested. This method was suggested by J. Y. Park, et al. in Micro-machined High Q Inductors for High Frequency Applications, Proc. SPIE, vol. 3514, 1998, pp. 218-228. The method repeatedly performs the steps of forming a polyimide layer as a plating mold, forming metal layer at a predetermined area which is defined by the polyimide layer, and forming seed metal layer on the entire surface of the polyimide layer and the metal layer. The disclosed method utilizes non-conductive polyimide as a plating mold. Therefore, the method should form a seed metal layer on each and every layer in order to plate upper surface of every polyimide material by using the seed metal layer. This increases the number of processes. Also, the polyimide layer is easily deformed by upper layer processes, such as, processes of seed metal deposition and upper layer lithography. Further, because of seed metal layers which remain between inductors and supporting members, the inductors are not so tightly adhered to the supporting member.
It is therefore a principal object of the invention to provide a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, by several tens of xcexcm, such that the overall area of the semiconductor device may be highly reduced.
It is an another object of the invention to provide a monolithic semiconductor device where a passive element having small series resistance and large capacity of current flow is integrated.
It is a further object of the invention to provide a method for manufacturing a monolithic semiconductor device having passive elements formed over a substrate which contains integrated circuits, wherein the passive elements have negligibly little influence on the integrated circuits.
In accordance With one aspect of the present invention to achieve the aforementioned object, a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate is provided. The method comprises the steps of forming a first metal layer on the substrate; forming a second metal layer on a portion of the first metal layer such that side surfaces of the second metal layer and an upper surface of other portion of the first metal layer on which the second metal layer is not formed define a recess; forming a third metal layer on the first and second metal layers such that a portion of the third metal layer is located on a predetermined portion of the second metal layer and other portion of the third metal layer fills the recess; removing the second metal layer; and removing a portion of the first metal layer which is not covered by the third metal layer.
In accordance with an another aspect of the present invention, a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate is provided. The method comprises the steps of: forming a first metal layer on the substrate; forming a first masking layer on a portion of the first metal layer; forming a second metal layer on other portion of the first metal layer on which the first masking layer is not formed; forming a second masking layer on the first masking layer and the second metal layer; removing the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer; forming a third metal layer on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer; removing the second masking layer; removing the second metal layer; and removing the first metal layer except a portion which the third metal layer covers.
In accordance with a further aspect of the present invention, a method for manufacturing a semiconductor device having a substrate and a metal layer formed over the substrate is provided. The method comprises forming a first metal layer 203 on the substrate 101; forming a first masking layer 204 on a portion of the first metal layer 203; forming a second metal layer 205 on other portion of the first metal layer 203 on which the first masking layer 204 is not formed; removing the first masking layer 204 to expose side surfaces of the second metal layer 205 and a surface of the portion of the first metal layer 203, such that the exposed surfaces define a recess; forming a third metal layer 102 on the first and second metal layers 203 and 205 such that the recess is filled with the third metal layer 102; removing a portion of the third metal layer 102 such that the portion which fills the recess is remained; forming a second masking layer 206 on the second and third metal layers 205 and 102; removing a portion of the second masking layer 206 which includes a portion which covers the third metal layer 102; forming a metal layer 102 on portions of the second and third metal layers 205 and 102 which are exposed by the step of removing the portion of the second masking layer 206; removing the second masking layer 204; removing the second metal layer 205; and removing a portion of the first metal layer 203 which is not covered by the third metal layer 102.